The present invention relates in general to a data processing system, and in particular, to high frequency I/O interface testing in a data processing system.
The increasing clock speeds in modem processor devices complicates the testing facilities for testing input/output (xe2x80x9cI/Oxe2x80x9d) interfaces. FIG. 1A illustrates an I/O interface 100 in accordance with prior art. Both input data and output data are presented on bidirectional data pin 102. Output data is received as launch data input 104 in output launch latch 106. The launch data is latched into latch 106 on an edge of clock 108, and is then provided to an input of buffer 110. An output of output buffer 110 is connected to bidirectional data pin 102. The output of output buffer 110 and bidirectional data pin 102 are coupled to an input of input buffer 112. Input data appearing on bidirectional data pin 102 is buffered by input buffer 112 and provided to input 114 of input capture latch 116. In this way, launch data also appears, albeit delayed in time due to synchronization and propagation delays in the circuitry, at input capture latch 116. Following set-up of the input data on input 114 of input capture latch 116, the data is latched on an edge of clock 108. The wrapping of launch data at input 104 from output launch latch 106 into capture data at output 118 from input capture latch 116 is used to test I/O interface 100.
FIG. 1B schematically illustrates a timing diagram of interface 100 for a first speed of clock 108 having a clock period longer than the propagation delays from output latch 106, through buffer 110, through buffer 112 and into input latch 116. Output data xe2x80x9caxe2x80x9d on launch data 104 is latched into output launch latch 106 on the rising edge, T1 of clock 108. Following clock edge T1, the next data xe2x80x9cbxe2x80x9d is set up on launch data 104, and latched into output launch latch 106 on edge T2 of clock 108, one clock period after edge T1. On the same edge, T2, data xe2x80x9caxe2x80x9d is captured in capture input latch 116. Data xe2x80x9caxe2x80x9d appears on input 114 of input capture latch 116 following a delay, Tdelay, which includes the propagation delays from output latch 106 through buffers 110 and 112.
In wrap I/O testing in accordance with the prior art, the speed of clock 108 is increased until launch data from output launch latch 106 is no longer captured in the same cycle in input capture latch 116. This occurs when, Tdelay plus the set-up time, typically non-negative, for input latch 116 exceed the clock period. FIG. 1C schematically illustrates a timing diagram for I/O interface 100 having a propagation delay exceeding the period of clock 108. Data to be launched is set up on launch data 104, and in the embodiment illustrated, is latched on the rising edge of clock 108. Data xe2x80x9caxe2x80x9d is launched on clock transition T1, and data xe2x80x9cbxe2x80x9d is launched on clock transition T2. After a propagation delay from output launch latch 106, the data is wrapped through buffer 110 and buffer 112 to input 114 of input latch 116. The data launched appears at input 114 after a propagation delay, Tdelay. In FIG. 1C, Tdelay plus the set-up time of input capture latch 116 exceeds the period of clock 108. Therefore, the data, for example data xe2x80x9caxe2x80x9d does not arrive at the input 114 of latch 116 in time for the next succeeding positive edge of clock 108, T2. In this case, the data launched in a given cycle, for example, data xe2x80x9caxe2x80x9d launched in cycle C0 is not captured in the same cycle, C0. Thus, in wrap I/O testing according to the prior art, the speed of clock 108 is increased until the data launched in a given clock cycle fails to be captured in the same cycle. This determines the limiting speed of I/O interface 100.
Wrap I/O testing in this way requires the tester to operate at the functional speed of I/O interface 100 under test. As the speed of data processing devices is increased, this requirement exceeds the capability of wrap I/O testers. Thus, there is a need in the art for apparatus and methods of testing of I/O interfaces at functional speeds that may exceed and are otherwise independent of the tester bus frequency.
The aforementioned needs are addressed by the present invention. Accordingly, there is provided, in a first form, an apparatus for wrap input/output (I/O) interface testing including a multiplexer operable for receiving first and second clock signals. The multiplexer is operable for selecting the first clock signal in response to a control signal asserted during I/O interface testing. A programmable delay unit is coupled to an output of the multiplexer. The programmable delay unit outputs a third clock signal operable for capturing an input data signal.
There is also provided, in a second form, a method of wrap I/O interface testing. The method includes the step of selecting a clock delay value, and launching a first data value in response to a first clock signal. The first clock signal is delayed by the clock delay value from the selecting step, thereby generating a second clock signal. A second data value is captured in response to the second clock signal.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.